Implementation of DSP and Communication Systems

This is a special issue published in volume 2002 of " EURASIP Journal on Applied Signal Processing. " All articles are open access articles distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. The telecommunications, wireless communications, multi-media, and consumer electronics industries are witnessing a rapid evolution toward integrating complete systems on a single chip. Single-chip systems will increasingly have both a hardware component as well as a software component, where the hardware component is of heterogeneous nature and may include a combination of ASIC, ASIP, digital signal processors, reconfigurable processors, FPGAs, and general processors. The architecture of digital signal processors has taken many new directions including VLIW, su-perscalar, SIMD, and more. The choice of the architecture styles and the hardware/software combination are determined by tradeoffs among costs, performance, power, time to market, and flexibility. Furthermore, the boundary between hardware and software has been blurred, while system design is characterized by ever-increasing complexity that has to be implemented within reduced time and resulting in minimum costs. Therefore computer-aided design tools that facilitate easy design process are of essential importance. The first paper proposes a lightweight floating point arithmetic, a family of customizable floating-point data formats, which bridges the design gap between software and hardware. The effectiveness of the proposed scheme is demonstrated using the inverse discrete cosine transform in the context of video coding. Such flexible data format will find applications beyond multimedia in areas such as wireless communication where a wide range of preci-sion/power/speed/area tradeoffs can be made. The second paper considers negative cycle detection in a weighted directed graph in the context of high-level synthesis for DSP systems. The paper introduces the concept of adaptive negative cycle detection and demonstrates the application of the technique for problems such as performance analysis and design space exploration in DSP applications. The third paper introduces a design environment FRIDGE, which supports transformation of signal processing algorithms coded in floating-point to a fixed-point representation. FRIDGE also provides a direct link to DSP implementation by processor specific C-code generation. The fourth paper presents a technique useful for efficient DSP processor compiler design, which reduces the CPU idle time due to the long memory access latency. The technique explores the instruction level parallelism among instructions of typical DSP applications. The next three papers deal with ASIC design of various …